To prevent the sampling processing of an analog circuit from being affected by pulse noise generated in a digital circuit in digital/analog IC.

Timing signals generated in the sampling timing generation part 12 of the digital circuit 11 are delayed and they are made into the sampling signals SP1-SP3 of the analog circuit 13. The digital circuit 11 is operated by a common master clock CK. The sampling pulses SP1-SP3 are supplied to the sampling processing part 14 of the analog circuit 13 through delay parts D1-D3 having same delay time τ as sampling pulses. Thus, the digital circuit 11 can execute the sampling processing at the inversion timing of the master clock CK without being affected by pulse noise since the operation timing of the pulses S1-S3 is delayed compared to noise pulses generated in power source lines VDD and VSS by the delay time τ of the delay circuits D1-D3.