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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5932024
Kind Code:
A
Abstract:

PURPOSE: To prevent a malfunction of an IC, by shifting the input power supply voltage by a prescribed level after transmitting the voltage through a level shifting circuit and generating a reset signal when the output voltage is less than the threshold value of a logical circuit.

CONSTITUTION: A level shifting circuit of an IC10' consists of an nMOS transistor TR11 forming a source follower and MOS diodes 12 and 13 which shift an input signal. Then this level shifting circuit shift the level of the input signal by 3VTHn (threshold voltage of nMOSTR). The voltage applied to an nMOS inverter 14 is set at Vs owing to the level shifting circuit. A PMOSTR of a Schmitt trigger is turned on during a rise of the power supply voltage and at a time point tA when the value of VS is turned to V1. Then an nMOSTR of the Schmitt trigger is turned on during a fall of the power supply voltage and at a time point tB when the value of MS is set at V2. In such a way, a reset signal is assuredly generated.


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Inventors:
SUGIE MAMORU
TOYOOKA TAKASHI
AOKI HIROKAZU
YOSHIDA KAZUTOSHI
CHIBA SHINSAKU
Application Number:
JP14151282A
Publication Date:
February 21, 1984
Filing Date:
August 13, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F1/24; G11C11/14; H03K17/22; (IPC1-7): G11C11/14
Domestic Patent References:
JPS5722254U1982-02-04
JPS5847927B21983-10-25
Attorney, Agent or Firm:
Masatoshi Isomura