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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED DEVICE
Document Type and Number:
Japanese Patent JPH03263368
Kind Code:
A
Abstract:

PURPOSE: To backward bias an isolation region even when some power supplies which are not turned on exist by a method wherein, in a semiconductor integrated device which is operated by a plurality of power supplies, the plurality of power supplies are connected in common to an electrode in the isolation region including a resistance diffusion layer separately via diodes.

CONSTITUTION: When potentials of power supplies V1 to Vn have a relationship of V1>...>Vn, generally all the power supplies are turned on normally. However, only a diode 151 connected to the power supply V1 whose potential is highest is turned on and all the remaining diodes 152 to 15n are turned off. Consequently, a voltage which has subtracted a forward drop voltage VD of the diode 151 from a potential of the power supply V1 is applied to an electrode 14 in an isolation region at this time; a resistance diffusion junction is normally backward biased. On the other hand, when the power supply V1 is not turned on by some cause and is at 0V, only the diode 152 connected to the power supply V2 whose potential is highest out of the remaining power supplies V2 to Vn is turned on. Thereby, the resistance diffusion junction is backward biased normally.


Inventors:
MATSUI TAKASHI
ENDO YOICHI
Application Number:
JP6162190A
Publication Date:
November 22, 1991
Filing Date:
March 13, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/04; H01L21/822; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)