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Title:
SEMICONDUCTOR INTEGRATED ELEMENT
Document Type and Number:
Japanese Patent JP2011091164
Kind Code:
A
Abstract:

To provide a semiconductor integrated element which can suppress connection loss of guided wave light without using a tapered region.

The semiconductor integrated element 1 includes a first clad layer C1, a second clad layer C2 having a first ridge part 15 and a second ridge part 25, a core region having a first core layer 10 and a second core layer 20 and formed between the first clad layer C1 and the second clad layer C2, and an embedded layer 6. A width of the first ridge part 15 is different from a width of the second ridge part 25. The first core layer 10 is connected to the second core layer 20 by a butt joint method. A first semiconductor optical element S1 includes the first clad layer C1, the first core layer 10, the second clad layer C2, a first adjusting layer A1, and the embedded layer 6. The first adjusting layer A1 is formed between the embedded layer 6 and the first ridge part 15, and extends in a predetermined axial direction while it is in contact with the first ridge part 15. A refractive index of the first adjusting layer A1 is lower than a refractive index of the first core layer 10 and is higher than a refractive index of the embedded layer 6.


Inventors:
HASHIMOTO JUNICHI
Application Number:
JP2009242721A
Publication Date:
May 06, 2011
Filing Date:
October 21, 2009
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H01S5/026; H01S5/12
Attorney, Agent or Firm:
Yoshiki Hasegawa
Shiro Terasaki
Yoshiki Kuroki
Ichira Kondo