Title:
SEMICONDUCTOR INTEGRATED LOGIC CIRCUIT AND NET LIST CONVERTING SYSTEM
Document Type and Number:
Japanese Patent JP2778443
Kind Code:
B2
Abstract:
PURPOSE: To preserve the state of a whole semiconductor integrated logic circuit when shifting operations are performed by connecting latch circuits to the outputs of flip flop circuits constituting a partial scan circuit when the logic circuit is connected to the control signal terminals of sequential circuits other than the flip flop circuit of a shift register circuit.
CONSTITUTION: Since the output of a flip flop(FF) 1 is connected to the clock terminal of an FF 9 which is a sequential circuit other than a scan path constitution, a latch circuit 7 is provided to store the output of the FF 1 so as to prevent the output from changing. Similarly, a latch circuit 8 is connected to the output of an FF 3. Since the output of an FF 2 is connected to the data terminal of an FF 10, no latch circuit is connected to the output of the FF 3. Similarly, no latch circuit is connected to the output of an FF (n). When such a circuit configuration is used, the state of a whole semiconductor integrated circuit is preserved even when shifting operations are performed for setting values against the FFs 1, 2,..., n.
Inventors:
OZAKI HIDEHARU
Application Number:
JP33602093A
Publication Date:
July 23, 1998
Filing Date:
December 28, 1993
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/3185; G06F11/22; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Domestic Patent References:
| JP6338179A | ||||
| JP63134970A | ||||
| JP273173A | ||||
| JP4113284A | ||||
| JP60111172A | ||||
| JP2126170A | ||||
| JP3252570A | ||||
| JP6338186A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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