PURPOSE: To reduce the area of a memory cell, by forming the memory cell, which is formed by two MOSFETs and an electrostatic capacitor, which is connected between the MOSFETs, by utilizing a groove shaped electrostatic capacitor.

CONSTITUTION: On a P+ type of N+ type semiconductor substrate 1 having high impurity concentration, a P-type epitaxial layer 2 is laminated and formed by an epitaxial growing method. A groove 4 is formed in the surface of the layer 2 at an element forming part so as to reach the Si substrate 1 by anisotropic etching. MOSFETs 8 and 9 are formed on both sides of the groove 4. The MOSFET 8 is constituted by an N+ region 10, which is extended to the side surface of the groove 4, another N+ region 11, which is separately provided on the surface of the layer 2, and a gate layer 14. The gate layer 14 comprises a poly Si layer 13, which is provided on a channel region 12 between both N+ regions 10 and 11 through a gate oxide film 5. Both N+ regions 10 and 15, which are extended to both side surfaces of the groove 4, form an electrostatic capacitor between capacitor electrodes 7. This structure is equivalent to the series circuits of the two electrostatic capacitors, which are formed between the MOSFETs.