Title:
SEMICONDUCTOR MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPH06103786
Kind Code:
A
Abstract:
PURPOSE: To increase speed of reading out a semiconductor memory.
CONSTITUTION: This circuit is constituted of a P type MOSFET Q1 connected between a power supply VDD and a first connecting point P1, P type MOSFET Q2 of which a source is connected to the first connecting point P1 and a gate is connected to a reference voltage terminal and a drain is connected to an output terminal of a memory cell array 20, and an inverter Iv of which an input terminal is connected to the first connecting point PI and an output terminal is connected to an output terminal Vo. Since voltage amplitude of a digit line D0 is decreased by the P type MOSFET Q1, speed of reading out a memory can be increased.
Inventors:
NARAHARA TETSUYA
Application Number:
JP25160892A
Publication Date:
April 15, 1994
Filing Date:
September 21, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/417; G11C16/06; G11C17/18; (IPC1-7): G11C11/417; G11C17/18
Attorney, Agent or Firm:
Yosuke Goto (2 outside)
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