PURPOSE: To reduce a semiconductor chip area by providing a horizontal group decoder and a vertical group decoder in an array and adding an OR circuit.

CONSTITUTION: The titled circuit is consisting of the horizontal group decoder 1 having the input of a high order column address 10 and the output of a horizontal group selection signal 12, a vertical group decoder 2 having the input of a low order column address 11 and the output of a vertical group selection signal 13, a horizontal group selection circuit 4 having the input of the horizontal group selection signal 12 and outputting the data of a bit line 3 to a horizontal group data output line 15, a vertical group selection circuit 5 having the input of the vertical group selection signal 13 and outputting the data of the bit line 3 to a vertical group data output line 16, the OR circuit 6 having the input of the horizontal group and the vertical group selection signals 12, 13 and the output of a bit line selection signal 14 and a switch 7 for connecting the bit line 3 and a data input/output signal line 17 by the bit line selection signal 14. The column address is divided into two sets and first and second decoders 1, 2 and the OR circuit are provided in the array, thereby, the number of wirings passing through the array is deleted and the semiconductor chip area can be reduced.