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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2006216136
Kind Code:
A
Abstract:

To provide a semiconductor memory device, capable of reducing the problem of an RC delay caused by the extension of a data line, such as a global data line or a local data line, and achieving high speed and large capacity for, e.g., an eDRAM constituted by stacking submacros.

The semiconductor memory device is constituted, in such a manner that a data control unit 13B connected to an interface section via global data lines RDL and WDL, a first memory block 13A constituted of a first memory cell array connected to one side of the data control unit via a first local data line DQt/c and a first sense amplifier section connected to this first memory cell array, and a second memory block 13C constituted of a second memory cell array connected to the other side of the data control unit 13B via a second local data line DQ/c and a second sense amplifier section connected to this second memory cell array are sequentially connected to the interface section to constitute a submacro 13.


Inventors:
KAKO MARIKO
Application Number:
JP2005026711A
Publication Date:
August 17, 2006
Filing Date:
February 02, 2005
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/409; G11C11/401
Domestic Patent References:
JPH11195766A1999-07-21
JP2006216137A2006-08-17
JP2003258125A2003-09-12
JP2000182370A2000-06-30
JPH10334662A1998-12-18
JP2003007062A2003-01-10
JP2004079077A2004-03-11
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto



 
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