To provide a semiconductor memory device in which symmetry in a sense amplifier is relaxed or not needed.

Two even and odd-number-th transfer gates (TG0_E, TG0_O), (TG1_E, TG1_O), (TG2_E, TG2_O), (TG3_E, TG3_O) connected in series are provided between end parts of adjacent bit lines (BL0, BL1), (BL1, BL2), (BL3, BL4) which are connected to bit lines of the sense amplifier and a memory cell array side. A first bit line (SA0_BL_TRUE) of the sense amplifier is connected to a connection point of the two even and odd-number-th transfer gates (TG0_E, TG0_O) between the bit lines (BL0, BL1) of a corresponding memory cell array, a second bit line (SA0_BL_BAR) of the sense amplifier is connected to a connection point of the two even and odd-number-th transfer gates (TG1_E, TG1_O) between two bit lines (BL1, BL2) of a corresponding memory cell array, control is performed so that one bit line out of a pair of bit lines of the sense amplifier is used as a signal side bit line by controlling two kinds of transfer gates.