To provide a semiconductor memory device for repairing a memory cell in which reset has failed.

The semiconductor memory device includes: a memory cell array MA including memory cells MC arranged at intersections of a plurality of bit lines BL and a plurality of word lines; and a control circuit 30 which applies reset pulses a plurality of number of times to a selected bit line BL and a selected word line in order to change a resistance state of a selected memory cell MC arranged at the intersection of the selected bit line Bl and the selected word line WL by applying a predetermined potential difference to the selected memory cell MC. The control circuit 30 applies a reset pulse more than once for changing the resistance state of the selected memory cell MC, and also performs repair operation, after applying the reset pulse, to apply pulse voltage having longer pulse width than the reset pulse to the memory cell MC whose resistance state has not been changed even after the reset pulse is applied the predetermined number of times.