Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2014203498
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a flash memory capable of suppressing power consumption and performing high-speed operation.SOLUTION: A flash memory 100 includes: a memory array 110; a word line selection circuit 160; a current detection type sense circuit 170 that is connected to each of the memory array and detects current that flows through a selected bit line; and erasure means that erases data of memory cells of a selected block in the memory array. The erasure means includes: an erasure sequence in which whether or not the current flowing through each of the bit lines of the block for which erasure has been performed is greater than a first value is determined and, if the current flowing through each of the bits is greater than the first value, erasure verification is completed; and a sequence in which a soft-program voltage is applied to all word lines of the block for which the erasure has been performed, soft-program verification for determining whether or not the current flowing through each of the bit lines is smaller than a second value is performed, and if the current flowing through each of the bit lines is smaller than the second value, the soft-program sequence is completed.
Inventors:
YANO MASARU
Application Number:
JP2013081020A
Publication Date:
October 27, 2014
Filing Date:
April 09, 2013
Export Citation:
Assignee:
WINBOND ELECTRONICS CORP
International Classes:
G11C16/02; G11C16/04; G11C16/06
Attorney, Agent or Firm:
Kyozo Katayose