Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3784301
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce power consumption of a whole device by suppressing charge and discharge current of a semiconductor memory device.
SOLUTION: A row direction selecting circuit RS selects the prescribed memory cell groups C11-Cp1, C12-Cp2,... in a row direction in accordance with a row input address signal. A column direction selecting circuit CS selects the prescribed memory cell groups C11-C1m, Cp1-Cpm,... in a column direction in accordance with a column input address signal. Intermittent circuits S1-Sp connect divided bit lines corresponding to columns selected by the column direction selecting circuit CS out of divided bit lines BL11-BLp1, BLX11-BLXp1 connected to each to the memory cell groups C11-Cp1, C12-Cp2,... selected by the row direction selecting circuit RS to corresponding common bit lines GBL1- GBLp, GBLX1-GBLXp.
Inventors:
Wataru Yokozeki
Application Number:
JP2001344484A
Publication Date:
June 07, 2006
Filing Date:
November 09, 2001
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/41; G11C11/417; G11C8/12; (IPC1-7): G11C11/417; G11C11/41
Domestic Patent References:
| JP2000011639A | ||||
| JP4370595A | ||||
| JP1179292A | ||||
| JP2000207886A |
Attorney, Agent or Firm:
Takeshi Hattori
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