PURPOSE: To shorten an access time by providing a means for making al word lines non-selective before the change of an address signal and thereby, reading data as soon as a selected memory cell can be read.

CONSTITUTION: A control clock signal CLK is changed from a high potential to a low potential at a time preceding to the change of the address signal. Then, the CLK goes a reference potential 81 set lower than the low potential of decoder input signals (a), (b) through a level shift circuit 93 and is inputted to the base of transistors 12, 17. Accordingly, irrespective of the high and the low potential of the decoder input signals (a), (b), transistors 11, 16 are made conductive, so that the base potential of word drivers WD1, WD2 are lowered, thereby, all word lines W1, W3... being set to a non-selective level. Thereby, when a certain memory cell MC1, MC2... can be read, the data thereof can be read to shorten the access time.