PURPOSE: To easily grasp the degraded state of a chip from an external part by successively selecting plural information to be stored in a storing means at the time of a test mode, counting the number of the information requiring error correction, and outputting the information to the external part.
CONSTITUTION: A test mode detection circuit 11, address switch 12, address counter 13, data counter 14 and data switch 15 are provided. When a test mode enable signal TE is applied from the external part to the test mode detection circuit 11, the test mode detection circuit 11 applies a test mode setting signal TS to the address switch 12, address counter 13 and data switch 15 and a semiconductor memory device is set to an internal test mode. The data switch 15 outputs the number of bytes corrected by a correcting circuit 10 from an I/O buffer 6 to the external part. Thus, the number of the information, which error is corrected, can be easily known from the external part of the chip and the degraded state of the chip can be easily grasped.
| JPS5819712 | DATA RECORDING SYSTEM |
| JPS5276838 | CONSTITUTION OF MEMORY |
| JPH08222639 | SEMICONDUCTOR DEVICE |
TERADA YASUSHI
HAYASHIGOE MASANORI
KOBAYASHI KAZUO
MIYAWAKI YOSHIKAZU
