To provide a semiconductor memory device in which the leakage defect of a bit line can be avoided with a simple circuit construction without lowering the voltage of the bit line.

A semiconductor memory device has bit lines and word lines which are laid vertically and horizontally, readable and writable memory cells 1, precharge MOS transistors Q1 and Q2, short-circuit MOS transistors Q3 and level setting MOS transistors Q4 and Q5. Two bit lines are provided for each bit. Three fuses F1-F3 for respective columns are connected between the precharge MOS transistors Q1 and Q2 and a bit line driving power supply terminal Vcc on their upstream side. If a leakage defect is produced in a bit line, all the fuses F1-F3 connected to that bit line are cut off. As a plurality of fuses are connected in parallel, a voltage drop between both the terminals of the fuses can be suppressed.