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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS5651875
Kind Code:
A
Abstract:

PURPOSE: To reduce the time requiring for writing by compensating a potential change in an insulating gate composing of a memory device by varying control gate potential wherein an injection current is always maintained at its maximum and a constant charge is injected.

CONSTITUTION: Main equipment, a matrix 11 serving as a memory device is provided with a Y decorder 12 and an X decorder 13. In addition to the above, a dummy decorder 14 corresponding to one bit and a dummy cell 15 and a potential control circuit 16 are provided. In this case, the dummy cell 15 has the same size as for a cell in the main equipment, matrix 11 and no insulating gate is provided. In this composition, when writing is applied, a cell channel current and the dummy cell 15 channel current selected from the Y decorder 12 and the dummy decorder 14 are compared by taking out potential to be monitored. And the potential of the X decorder 13 which is control potential for the selected cell is controlled by using the circuit 16 to decide the pontential for maximum injection current to the cell. In this way, the time required for writing is reduce.


Inventors:
WADA MASASHI
Application Number:
JP12728979A
Publication Date:
May 09, 1981
Filing Date:
October 04, 1979
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/112; G11C16/04; G11C16/12; G11C17/00; H01L21/8246; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; H01L27/10; H01L29/78