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Title:
SEMICONDUCTOR MEMORY HAVING IMPROVED LATCH-TYPE REPEATER FOR SELECTING MEMORY ROW LINE
Document Type and Number:
Japanese Patent JPH05266668
Kind Code:
A
Abstract:

PURPOSE: To save power consumption by improving a latch-type repeater.

CONSTITUTION: Row line repeaters 16 are arranged between respective divided sub-arrays, so that a row line from a row decoder 14 or from the preceding sub-array is linked to the succeeding sub-array. The row line repeaters 16 are controlled, in accordance with a part of a column address, and the whole selected rows are energized and, after that, the row line repeaters which are not related to the selected sub-array deenergizes the row line in their output ends. The respective row line repeaters 16 are provided with a latch and, therefore, the row line repeaters 16 which are not related to the selected sub-array keep the selected row line in an energizing state. Another kind of control of the row line repeater from a power-on-reset circuit 24 is executed. A dummy row line DRL is also provided; it emulates the actual row line and, therefore, a time when the selected row is perfectly energized is discriminated more precisely.


Inventors:
David Charles McClure
Application Number:
JP24544691A
Publication Date:
October 15, 1993
Filing Date:
September 25, 1991
Export Citation:
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Assignee:
SGS-Thomson Microelectronics Incorporated
International Classes:
G11C8/00; G11C8/06; G11C8/08; G11C8/14; G11C8/18; G11C11/407; G11C11/41; G11C16/06; G11C17/00; (IPC1-7): G11C11/41; G11C8/00; G11C11/401; G11C16/06
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)