PURPOSE: To save power consumption by improving a latch-type repeater.
CONSTITUTION: Row line repeaters 16 are arranged between respective divided sub-arrays, so that a row line from a row decoder 14 or from the preceding sub-array is linked to the succeeding sub-array. The row line repeaters 16 are controlled, in accordance with a part of a column address, and the whole selected rows are energized and, after that, the row line repeaters which are not related to the selected sub-array deenergizes the row line in their output ends. The respective row line repeaters 16 are provided with a latch and, therefore, the row line repeaters 16 which are not related to the selected sub-array keep the selected row line in an energizing state. Another kind of control of the row line repeater from a power-on-reset circuit 24 is executed. A dummy row line DRL is also provided; it emulates the actual row line and, therefore, a time when the selected row is perfectly energized is discriminated more precisely.
Next Patent: SEMICONDUCTOR MEMORY HAVING SEQUENCE-TYPE AND LATCH-TYPE ROW LINE REPEATER