SEMICONDUCTOR MEMORY, ITS MANUFACTURING METHOD, AND TEST DEVICE THEREFOR

Title:

SEMICONDUCTOR MEMORY, ITS MANUFACTURING METHOD, AND TEST DEVICE THEREFOR

Document Type and Number:

Japanese Patent JP2000331495

Kind Code:

A

Abstract:

To perform tester relief in a short time without increasing the number of signal lines in the inside of a tester by inputting defective bit addresses to plural chips by time-sharing, and performing simultaneously cut off of a fuse or a anti-fuse using a power source prepared independently for each chip.

A power source VCCA for internal circuit, a power source VCCB for anti-fuse, and a ground power source VSS are connected independently to a power source. First, a tester activates a SEL0, and outputs an anti-fuse set address af0 OF A chip #0 to an address line A (0:11). Successively, the tester outputs a defective bit address ax0 written in an anti-fuse set to A (0:11). At the time. the chip #0 latches af0 and ax0. After one group of af and ax is latched to each chip, SEL0 to SEL31 are all activated, anti-fuse sets are cut off in all chips. After that, SEL0 to SEL31 are all activated.

Inventors:

SEKIGUCHI TOMONORI
TAKAHASHI TSUGIO
SAKATA TAKESHI
NAGASHIMA YASUSHI
KIMURA KATSUTAKA
MURAKAMI KYOKO
NANBA MASAAKI
KINOSHITA YOSHITAKA

Application Number:

JP13824099A

Publication Date:

November 30, 2000

Filing Date:

May 19, 1999

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

G11C29/00; G11C29/04; G11C29/44; G01R31/28; G11C29/56; (IPC1-7): G11C29/00; G11C29/00; G01R31/28

Attorney, Agent or Firm:

Sakuta Yasuo

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