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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2001167580
Kind Code:
A
Abstract:

To reduce a noise without completely degrading a high speed characteristic.

When two data of double data specification outputted from the same output terminal at the same cycle are read out from a memory cell array, by providing a delay circuit at one side of a sense amplifier enable-signal /SAE, a sense amplifier 1 and a sense amplifier 2 are activated, timing at which two data are sensed is deviated, peak current flowing in the sense amplifier 1 and the sense amplifier 2 is deviated. Furthermore, a generation level of a noise can be reduced without completely degrading read-out speed by making a deviation time a half cycle of an operation clock or less.


Inventors:
HIRABAYASHI OSAMU
Application Number:
JP34805599A
Publication Date:
June 22, 2001
Filing Date:
December 07, 1999
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/417; G11C7/06; G11C7/10; G11C11/407; G11C11/409; G11C11/41; G11C11/413; (IPC1-7): G11C11/417
Attorney, Agent or Firm:
Hidekazu Miyoshi (7 outside)



 
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