To provide a semiconductor memory in which a control signal by CAS latency is generated, power down of a BDD circuit (or SMD circuit) can be performed as a power down signal, and power consumption can be reduced at the time of active power down.

This memory is provided with a clock initial stage circuits 1, 2 to which clock signals CLK, CLKB are inputted respectively, an output circuit 24 synchronizing with an external clock signal and outputting data stored in a memory cell by a BDD signal BDD0 generated based on this external input signal, a delay quantity adjusting circuit constituted of replica circuits 3, 4, 9, 10 and delay line circuits of delay lines 17-20 or the like in which output phase difference between a clock signal CLK generated by delay of the CLK initial stage circuits 1, 2 and an output circuit 24 and data is corrected by delaying the BDD signal BDD0, synchronism of the clock signal CLK and the data is obtained, and a control circuit 25 controlling operation and stop of these delay circuits.