Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3312574
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a word line potential is controlled to an optimum value for variation of a threshold value of a memory cell transistor in a manufacturing process and stable read-out is guaranteed.
SOLUTION: A detecting cell transistor having the same structure as a memory cell transistor in a memory cell array 10 is connected to each word line W, and word lines W are controlled by detecting their conduction or non- conduction by detecting amplifiers 61-63. As the detecting cell transistor is equivalent to a memory cell, even if a threshold value of the memory cell transistor is varied, a word line potential can be controlled to an optimum value for read-out. Also, stable read-out is guaranteed by deciding latch timing of data depending on conduction or non-conduction of the detecting cell transistor, while the number of circuits is suppressed, and an area of a chip can be reduced.
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Inventors:
Kenji Hibino
Application Number:
JP6431597A
Publication Date:
August 12, 2002
Filing Date:
March 18, 1997
Export Citation:
Assignee:
NEC
International Classes:
G11C16/06; G11C16/02; G11C16/04; H01L21/8246; H01L27/112; (IPC1-7): G11C16/04; G11C16/02
Domestic Patent References:
| JP8297983A | ||||
| JP62257699A |
Attorney, Agent or Firm:
Takao Maruyama