Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3955932
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a wrong setting by providing a setting means for setting write-prohibition/permission information and setting write-prohibition information to a memory element at a write cycle after a plurality of predetermined read cycles.
SOLUTION: Bit lines BL, /BL selected by a column decoder Y-dec are fixed to an exclusive OR according to write data fed to common input/output lines IO, IOB. Thereafter, a word line WL selected by a row decoder X-dec is turned to a high level and, MOS transistors Q1, Q2 are connected. At this time, a ferroelectric capacitor C2 connected to the bit line /BL is not polarized nor inverted because a plate line PL and the line /BL are at a low level, and holds the present data as they are. In contrast, a ferroelectric capacitor C1 is polarized and inverted in the direction because the like PL is at the low level and the like BL is at the high level. Data are accordingly written to the capacitor C1.
Inventors:
Yoshihiko Yasu
Hiroyuki Sakai
Michael W. Jaeger
Donald Jay Verhey
Hiroyuki Sakai
Michael W. Jaeger
Donald Jay Verhey
Application Number:
JP6949197A
Publication Date:
August 08, 2007
Filing Date:
March 24, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
Ramtron International Corporation
Ramtron International Corporation
International Classes:
G11C16/02; G06F12/14; G06F21/60; G06F21/62; G06F21/79; G06F21/81; G11C7/24; G11C11/22; (IPC1-7): G11C16/02
Domestic Patent References:
| JP5120891A | ||||
| JP7114497A | ||||
| JP7122077A | ||||
| JP5088985A | ||||
| JP56134400A | ||||
| JP60150285A | ||||
| JP59171100A | ||||
| JP5074169A |
Attorney, Agent or Firm:
Yamato Tsutsui