To reduce the power consumption of a semiconductor memory by eliminating the need of a boosting circuit and a high-voltage generating circuit for driving word lines by obtaining a word line driving voltage by supplying an external power supply voltage to a word line driver.
When a prescribed row address is transmitted from a row address buffer, a row address decoder 2 decodes the row address and one word line WL is selected out of a large number of word lines in accordance with the decoded row address. An external power supply voltage is supplied to an internal power supply voltage generating circuit 8 and a word line driver 4 and the circuit converts the supplied voltage into an external power supply voltage and outputs the external power supply voltage to an internal circuit. The word line driver 4 which receives the external power supply voltage transmits the inputted external power supply voltage to the selected work line WL in accordance with the output of the decoder 2.
JPS6476493 | SEMICONDUCTOR MEMORY DEVICE |
JPH0963299 | SEMICONDUCTOR MEMORY |
JP2014071916 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY VOLTAGE CONTROL METHOD |
CHO HIDEHITO
JPS62178013A | 1987-08-05 |
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