To improve the speed of response of the output signal of a high-speed counter circuit to inputted clock signals by operating a highest-order bit counter and a lowest-order bit counter synchronously to the clock signals.

First to sixth bit counters 30, 32, 34, 36, 38, and 40 operate synchronously to a clock signal and generate count values at the timing which is delayed from the trailing edge of a clock signal by about the propagating time by means of one AND gate and one bit counter. Therefore, the delay time from the clock signal to the generating timing the count values can be minimized and, at the same time, the count values can be easily matched to the output values of other circuits.