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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS63168900
Kind Code:
A
Abstract:

PURPOSE: To prepare many spare cells without increasing the size of chips by using a means for selecting one combination signal corresponding to a defective word line out of the output of a partial decoding means.

CONSTITUTION: A partial decoding means D01 obtains all main and auxiliary combination signals of at least 2 bits based on address signals X1 and X2. A selection means S01 selects one combination signal corresponding to a defective word line out of the output of the means D01. The means D01 can be shared for selection of both word and spare word lines. Therefore, the means S01 is not required to decode partly the signals X1 and X2 just by selecting the relevant combination signal. As a result, the wiring area is extremely reduced and many spare cells can be provided.


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Inventors:
TSUJIMOTO JUNICHI
MATSUI MASAKI
OTANI TAKAYUKI
IWAI HIROSHI
Application Number:
JP83287A
Publication Date:
July 12, 1988
Filing Date:
January 06, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/401; G11C11/408; G11C29/00; G11C29/04; (IPC1-7): G11C11/34; G11C29/00
Domestic Patent References:
JPS6177946A1986-04-21
JPS60191500A1985-09-28
JPH0427639A1992-01-30
Attorney, Agent or Firm:
Takehiko Suzue



 
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