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Title:
SEMICONDUCTOR NON-VOLATILE MEMORY
Document Type and Number:
Japanese Patent JPH06290591
Kind Code:
A
Abstract:

PURPOSE: To make the adoption of a folded bit line system possible by connecting respectively a word line and a bit line, a word line and an anti-bit line to a memory cell and adjusting potentials of a bit line and an anti-bit line at the time of reading as required in a differential type sense system.

CONSTITUTION: In the differential type sense system to which a bit line BL and anti-bit line BL- are connected in parallel, memory cells MC1, MC2 are respectively connected to a word line WL and a bit line BL, a word line and an anti-bit line BL-. When potentials of the bit line BL and the anti-bit line BL- being the same potential at the time of pre-charge are set so as to have a difference between them, the memory cell MC1 or the MC2 is read out, a folded bit line system can be adopted, and reading operation and the like can be performed at high speed.


Inventors:
ARAKAWA HIDEKI
Application Number:
JP9730693A
Publication Date:
October 18, 1994
Filing Date:
March 31, 1993
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C17/00; G11C16/04; G11C16/06; G11C16/28; H01L21/8247; H01L27/115; (IPC1-7): G11C16/06; H01L27/115
Attorney, Agent or Firm:
Takahisa Sato



 
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