Title:
半導体出力回路
Document Type and Number:
Japanese Patent JP4229804
Kind Code:
B2
Abstract:
A NMOS (34a) determines whether output voltage (Vo) exists in state of power supply voltage (Vcc). When output voltage is same as supply voltage, NMOS (37) discharges electric charge of gate of source follower (32) based on control signal (c) that switches follower from ON state to OFF state. When output voltage is lower than supply voltage, another NMOS (39E) discharges charge of gate at lower rate than the NMOS (37).
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Inventors:
Akihiro Nakahara
Soma Osamu
Soma Osamu
Application Number:
JP2003364456A
Publication Date:
February 25, 2009
Filing Date:
October 24, 2003
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
H02M1/08; H03K17/04; H03K4/00; H03K17/0412; H03K17/16; H03K17/687; H03K19/0175
Domestic Patent References:
| JP3198421A | ||||
| JP6318854A | ||||
| JP661826A | ||||
| JP10200388A | ||||
| JP2002290221A |
Attorney, Agent or Firm:
Seisei Nishimura
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