Title:
半導体パッケージ
Document Type and Number:
Japanese Patent JP7003194
Kind Code:
B2
Abstract:
To provide a semiconductor package in which delay and ringing are suppressed, and a normally-off transistor and a normally-on transistor are cascode-connected.SOLUTION: A semiconductor package 200 includes a normally-off transistor 10, a normally-on transistor 20 connected to a drain 12, a capacitor 30 having an end part 32 connected to a gate 23, a diode 40 having an anode 41 connected between the end part 32 and the gate 23, a resistor 48 connected between an end part 31 and a gate 13, a diode 44 including an anode 45 connected to the end part 31 and provided in parallel to the resistor 48, a second capacitor 80 having an end part 82 connected to a source 21, a drain terminal 52 connected to a drain 22, a gate terminal 54 connected to the end part 31, the resistor 48, and the anode 45, a first source terminal 50 connected to a source 15, and a second source terminal 56 connected to an end part 81.SELECTED DRAWING: Figure 9
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Inventors:
Kentaro Ikeda
Application Number:
JP2020131498A
Publication Date:
January 20, 2022
Filing Date:
August 03, 2020
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K17/16; H01L23/48; H02M1/08; H03K17/00; H03K17/687
Domestic Patent References:
| JP2016019112A | ||||
| JP2012212875A | ||||
| JP2014512765A |
Foreign References:
| WO2017010554A1 |
Attorney, Agent or Firm:
Torushin Ikegami
Akira Sudo
Masahiro Takashita
Akira Sudo
Masahiro Takashita