半導体記憶装置 - 富士通株式会社

Title:

半導体記憶装置

Document Type and Number:

Japanese Patent JP5282430

Kind Code:

B2

Abstract:

This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, and a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage. Further, the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data.

More Like This:

JPH07112015	[Title of Invention] Semiconductor integrated circuit device and method for manufacturing the same
WO/1993/019468	FLASH-CLEAR OF RAM ARRAY USING PARTIAL RESET MECHANISM
WO/2017/122497	SEMICONDUCTOR CIRCUIT, DRIVING METHOD, AND ELECTRONIC DEVICE

Inventors:

Hirotoshi Sasaki

Application Number:

JP2008082673A

Publication Date:

September 04, 2013

Filing Date:

March 27, 2008

Export Citation:

Click for automatic bibliography generation Help

Assignee:

富士通株式会社

International Classes:

G11C11/412; G11C11/413

Domestic Patent References:

JP2002093176A
JP2005025863A
JP7057469A
JP6203564A
JP6215576A

Attorney, Agent or Firm:

Kenji Doi
Hayashi Tsunetoku

Previous Patent: SELENIUM PHOTOSENSITIVE BODY

Next Patent: ENVIRONMENT RECOGNIZING DEVICE FOR MOBILE VEHICLE