SEMICONDUCTOR TESTING DEVICE AND ADJUSTING METHOD THEREFOR

Title:

SEMICONDUCTOR TESTING DEVICE AND ADJUSTING METHOD THEREFOR

Document Type and Number:

Japanese Patent JP2008122180

Kind Code:

A

Abstract:

To provide a semiconductor testing device and its adjusting method capable of adjusting the timing with high accuracy, and in a short time.

A semiconductor testing device 1 comprises the semiconductor testing device body 2, a plurality of replaceable adjustment tools 3a, and a switching device 4. The semiconductor testing device main body 2 comprises a plurality of driver pin blocks 11a-11n for outputting a signal, given to a signal input pin of a device to be tested; and a plurality of IO pin blocks 12a-12n for outputting a signal, given to a signal input/output pin of the device to be tested and measuring the signal outputted from the signal input/output pin. The adjustment tools 3a make signal output terminals 34a-34n of the driver pin blocks 11a-11n, signal output terminals 44a-44n of the IO pin blocks 12a-12n, and signal input terminals 45a-45n go into a predetermined connected state.

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Inventors:

OTAKI TOSHIYUKI

Application Number:

JP2006305183A

Publication Date:

May 29, 2008

Filing Date:

November 10, 2006

Export Citation:

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Assignee:

YOKOGAWA ELECTRIC CORP

International Classes:

G01R31/3183

Attorney, Agent or Firm:

Masatake Shiga
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama

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