PURPOSE: To preform processing such that a change value due to a clock pulse exerts no effect on a value before application by dividing and allotting the logical values of each combination logical element and each FF of a circuit at every clock pulse.
CONSTITUTION: A delay test applying test clock pulses 1, 2 is considered. In order to set the output of an FF 53 to 10X by applying a falling change signal to an AND gate 58, the FF 53 requires the application of the pulse 1 and a data input value 1XX. Subsequently, when 11X is applied to the gate 58, since the pulse 1 is applied, an FF 54 calculates an output value 1XX in an AND gate 57. Further, since the output value of the AND gate 58 is 10X, 10X also appears in the gate 57 and the output of an FF 52 also requires 1XX and the output value of the gate 57 becomes 10X. Further, the clock pulse 2 is applied to a clock input edge pin 501 and the output quantity of an FF 55 is set to 110. When there is trouble, the output values of the gates 58, 57 become 11X and the output value of the FF 55 becomes 111 and these values are different from respective normal values. By this method, a test pattern can be formed without generating the mismatching of a logical value.
HATAKEYAMA KAZUMI
HAYASHI TERUMINE
