To easily generate test patterns in the simultaneous test of an LSI memory part and a lock part by independently describing the test patterns for testing both the logic part and the memory part.

A random pattern generating part 13 reads an instruction from an instruction memory 9 by a random pattern instruction executing part 10 when the memory part and logic part of an LSI are simultaneously tested, and reads a random pattern instruction from a random pattern memory 1. An ALPG instruction executing part 8 reads an instruction from an ALPG instruction memory 2, outputs an address data pattern from the ALPG 3 to an OR gate 11, and outputs a test random pattern from a memory test pin random pattern memory 7 to the gate 11. The gate 11 combines the data with the pattern and selects a prescribed pin to be applied by a pin selector 4. Thus, the memory test pattern can be described without being conscious of the logic capacity.