To operate the sequence control as the whole at a double speed by using a sequence means for simultaneously executing two instructions of sequence control.

This device comprises a frequency divider 190 for outputting halved frequency clocks obtained by halving a standard clock, a means for simultaneously executing two instructions of the microprogram of a sequence control part by the divided clocks, and a pattern generator for a high-speed converting part 160 for dividing the resulting output data of the simultaneous executions to the first and latter periods of the divided clocks, and outputting them synchronously with the standard clock. Two sequence controls can be executed during one divided clock cycle by providing the two-instruction simultaneously executing means, the high-speed converting means and a sequence control means for simultaneously executing two operation codes. A high-speed PC signal 105 obtained by retiming it with the standard clock is supplied to a pattern generating part 200, whereby a double-speed sequence control can be realized, and an old pattern program is also usable.