Title:
SIGNAL CHANGE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH09246927
Kind Code:
A
Abstract:
To provide a signal change detection circuit capable of surely generating signal change detection pulses.
Address signals AD which enter an address transition detection node 10 are directly inputted to one input terminal of an exclusive OR circuit 12, inverted through a delay circuit 11 composed of the plural stages of inverters 11a-11c and inputted to the other input terminal. A Schmitt trigger type inverter provided with hysteresis characteristics is used as an initial stage inverter 11a among the inverters 11a-11c for constituting the delay circuit 11 and sure address transition detection pulses are generated.
Inventors:
MITSUOKA KUNIHIKO
Application Number:
JP5524096A
Publication Date:
September 19, 1997
Filing Date:
March 12, 1996
Export Citation:
Assignee:
YAMAHA CORP
International Classes:
H01L21/8234; H01L27/088; H03K5/19; (IPC1-7): H03K5/19; H01L21/8234; H01L27/088
Attorney, Agent or Firm:
Itami Masaru