Title:
SIGNAL DELAY TIME CALCULATING METHOD, CLOCK SIGNAL REWIRING METHOD AND CELL ARRANGING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3599531
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To calculate signal delay time that is closer to an actual delay value of a manufactured chip by considering skew that is caused by the deviation of processes at the time of manufacturing.
SOLUTION: Path delay Tpd from a start point flip-flop to an end point flip-flop which configures a first path is calculated based on logical information and wiring pattern information which are inputted (S102). Respective delays Tck1 and Tck2 of clock wiring paths from a clock input pin of a chip to the start and end point flip-flops, delays Tckp1 and Tckp2 which are parts are parts that are not shared in the clock wiring paths and the finite difference Tskew= &verbar Tck1-Tck2&verbar of clock delay are respectively calculated (S103 to S105). Signal delay time Ttotal about the path is calculated by calculating the deviations Tpskew1 = αTckp1 and Tpskew2 = αTckp2 of clock delay about respective start and end point flip-flops which are caused by the deviation of processes at the time of manufacturing (S106).
Inventors:
Hiromitsu Yamada
Tetsuo Sasaki
Katsuki Suzuki
Tetsuo Sasaki
Katsuki Suzuki
Application Number:
JP19229397A
Publication Date:
December 08, 2004
Filing Date:
July 17, 1997
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP8129568A | ||||
| JP4211872A | ||||
| JP7114580A |
Attorney, Agent or Firm:
Makoto Suzuki