To always keep a good receiving state by placing a higher harmonic component reduction circuit in a signal processing circuit for suppressing the harmonic noises.

The harmonic component level is limited by a higher harmonic component reduction circuit 3 for the clock signal that has undergone its waveform shaping via a waveform shaper 2. Based on this clock signal, a CPU core part 4 performs the signal processing, according to the contents of a program ROM 5. The cut-off frequency of the circuit 3 is set at a level sufficiently higher than the frequency of the clock signal, to secure an operating margin and also set at a level sufficiently lower than the receiving frequency band of an equipment, including a receiving device for securing the attenuation of a higher harmonic component. Thus, it is possible to obtain a signal processing circuit which suppresses the undesired radiation and does not deteriorate the receiving performance by limiting the higher harmonic component level of the clock signal via the circuit 3.