PURPOSE: To improve the availability of a signal processing system by inserting automatically an idle instruction between two instructions to realize the switching between a pipeline process and a sequential process.

CONSTITUTION: An instruction received from a ROM 2 is sent to a 1st instruction register 3 with an address received from a program counter 1 and then successively to instruction registers 4, 5 and so on in the sequential machine cycles. The instructions sent from registers 3, 4... are supplied to a decoder 10 and executed. A selector 11 functions to select an idle instruction when no significant signal exists between the ROM 2 and the register 3. A significant signal output means 12 of the decoder 10 usually outputs an insignificant signal and then a significant signal when a real instruction is carried out. The output of the significant signal is supplied to a counter 1 via a switch SW 1 and also to the selector 11 via a one machine cycle delay circuit 13 and a switch SW 2. Thus it is possible to attain the switch between a pipeline process and a sequential process and the availability is improved with a signal processing system.