Title:
SILICON SINGLE CRYSTAL WAFER AND ITS PRODUCTION
Document Type and Number:
Japanese Patent JP3943717
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To produce the silicon single crystal wafer in which latent nuclei of OSF(oxidation induced stacking faults) or ring-shaped OSF, that are to be caused at the time of subjecting the wafer to thermal oxidation treatment, are present in an extremely low density, however, any FPD(flow pattern defect), COP(crystal originated particle), L/D(large dislocation), LSTD (laser scattering tomography defect) or defect detected by Cu decoration, is not present throughout the whole surface of the wafer, under stable production conditions by using a CZ (Czochralski) method.
SOLUTION: In the production of a single crystal used as this wafer by using a CZ method, at the time of growing the single crystal, the single crystal is pulled up while controlling the furnace inside temp. so that ΔG is 0 or a negative value (wherein: G (°C/cm) is the temp. gradient ((the amount of change in temp.)/(length in the direction of the crystal axis)) in the vicinity of a solid-liquid interface in the crystal, within the temp. range of from the melting point to 1,400°C; Gc (°C/cm) is the temp. gradient in the central part of the crystal; Ge (°C/cm) is the temp. gradient in the peripheral part of the crystal; and ΔG is the difference between Ge and Gc, i.e., ΔG=(Ge-Gc), and also controlling the single crystal pulling-up rate so as to fall within the range of from a pulling-up rate corresponding to the minimum value on the inner border line of the OSF region to a pulling-up rate corresponding to the minimum value on the outer border line of the OSF region, when an OSF region in the form of an inverted M-shaped belt is formed in a defect distribution diagram showing crystal defect distribution plotted with the crystal diameter and the crystal pulling-up rate as the abscissa and the ordinate respectively.
Inventors:
Masahiro Sakurada
Hideki Yamanaka
Tomohiko Ota
Hideki Yamanaka
Tomohiko Ota
Application Number:
JP17971098A
Publication Date:
July 11, 2007
Filing Date:
June 11, 1998
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
C30B15/22; C30B15/00; C30B15/14; C30B15/20; C30B29/06; G01N21/00; G01N21/27; G01N21/88; G05D23/19; H01L21/208; H01L21/66; (IPC1-7): C30B15/22; C30B29/06; G05D23/19; H01L21/208; H01L21/66
Domestic Patent References:
| JP8330316A |
Attorney, Agent or Firm:
Mikio Yoshimiya
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