Title:
SNUBBER CIRCUIT AND POWER CONVERTER EMPLOYING IT
Document Type and Number:
Japanese Patent JP3199610
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a snubber circuit for switching element in while the load current control performance can be enhanced while satisfying both the enhancement of overvoltage suppression effect and low loss.
SOLUTION: A series circuit of a first snubber diode Ds1 and a first capacitor C1 is connected between the input and output terminals of an IGBTQ1 and a charge/discharge circuit means, comprising a second capacitor C2, a second snubber diode Ds2, and at resistor R1, is connected in parallel with the Ds1. When the IGBTQ1 is turned on, a closed circuit is formed starting from the C1, passing through the IGBTQ1 and charge/discharge circuit means, and returning to the C1. Consequently, the C2 in charge/discharge circuit means is charged and the Ds1 is biased reversely with the charging voltage while the C1 is discharged when the IGBTQ1 is turned off. Consequently, a same current can be interrupted while reducing the voltage to be applied to the IGBTQ1 as compare with a prior art snubber circuit and the capacitor in snubber circuit can be discharged while reducing the loss.
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Inventors:
Hideki Miyazaki
Shin Kimura
Hideo Kobayashi
Shigeru Sugiyama
Shin Kimura
Hideo Kobayashi
Shigeru Sugiyama
Application Number:
JP19753795A
Publication Date:
August 20, 2001
Filing Date:
August 02, 1995
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H02M1/00; H03K17/16; (IPC1-7): H02M1/00; H03K17/16
Domestic Patent References:
| JP56166634A |
Attorney, Agent or Firm:
Kiyoshi Maruyama (7 outside)