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Patent Searching and Data


Title:
SOLDERING FOR SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS6351663
Kind Code:
A
Abstract:

PURPOSE: To permit a soldering work of a laminated material without generating a void between semiconductor wafers as well as to dispense with a heating oven for preheating the laminated material by a method wherein the laminated material formed by a way, wherein solder small plates are each interposed between the semiconductor wafers and voids are each formed between the semiconductor wafers, is dipped while being preheated by a fused solder.

CONSTITUTION: A laminated material 2 is formed by stacking semiconductor wafers 1 while solder small plates 5, whose areas are sufficiently small compared to those of the semiconductor wafers 1, are each interposed between the wafers. The semiconductor wafers 1 in a state that they are dipped slightly inner side of the surface of a fused solder 4 almost of not have a temperature gradient and the laminated material 2 is dipped in the fused solder 4 at such a descending speed that can make its temperature roughly equal to that of the fused solder 4. There is a void as large as the thicknesses of the solder small plates 5 due to the interposition of the solder small plates 5 between the semiconductor wafers 1 and as the laminated material 2 is lowered at roughly a constant speed for being dipped in the fused solder 4, the fused solder 4 exhausts the air and gas in the voids between the semiconductor wafers 1 and easily intrudes into the voids. With the laminated material 2 almost all dipped in the fused solder 4, the solder small plates 5 between the semiconductor wafers 1 are fused.


Inventors:
NAKAMURA TSUYOSHI
NAGAI TETSUO
MIZUNO KUNIJI
Application Number:
JP19480986A
Publication Date:
March 04, 1988
Filing Date:
August 20, 1986
Export Citation:
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Assignee:
ORIGIN ELECTRIC
International Classes:
H01L25/07; (IPC1-7): H01L25/08