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Title:
SOLID-STATE IMAGING ELEMENT
Document Type and Number:
Japanese Patent JP2004303982
Kind Code:
A
Abstract:

To provide a solid-state imaging element for attaining the compatibility of reduction in a read voltage and the improvement of a transfer efficiency.

A p-type well 507 is formed on an n-type semiconductor substrate 506, a CCD channel region 102 is formed on a surface region of the p-type well, a gate insulation film 510 is formed on the surface of the CCD channel region, a first electric charge transfer electrode 503 is formed on the gate insulation film, an inter-layer insulation film 511 is formed around the first electric charge transfer electrode, and a second electric charge transfer electrode 504 is formed in the gap of the first electric charge transfer electrode on the gate insulation film. The electrode length L1 of the second electric charge transfer electrode is longer than the electrode length L2 of the first electric charge transfer electrode, and an n--type potential step difference region 113 is formed to an upperstream side of the CCD channel region under the second electric charge transfer electrode by ion implantation of a p-type impurity.


Inventors:
YAMADA TORU
Application Number:
JP2003095926A
Publication Date:
October 28, 2004
Filing Date:
March 31, 2003
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L27/148; H01L27/146; H01L27/15; H01L31/10; H04N5/335; H04N5/341; H04N5/369; H04N5/372; (IPC1-7): H01L27/148; H04N5/335
Attorney, Agent or Firm:
Ikeuchi, Sato & Partners