To provide a source clock regenerating circuit adopting the SRTS system on a receiver side in an ATM transmission network that is realized by a general-purpose circuit when a user clock and a network extract clock with an ultrahigh speed are adopted.
The source clock recovery circuit is configured to include: a coincidence detection mask generating circuit comprising a final value generating section for generating each timing of a final value of an RTS period by a mask counter for counting an output resulting from 1/m frequency-dividing a network clock and of counts before and after the final value and a mask release value calculation section for receiving a received RTS value in the timing of RTS value coincidence detection and predicting a succeeding RTS value to generate a mask release output; and an RTS coincidence detection circuit comprising a mask logic section for introducing a succeeding mask release point by a logic arithmetic operation between a count of a 4-bit counter for counting the network clock and each signal from the final value generating section and generating a coincidence output between an output resulting from comparing the output of the 4-bit counter and a received RTS value and the mask release signal from the mask logic section.
Akira Yamatani
Yoshiyoshi Ogasawara