Title:
MULTIPLEXER AND DEMULTIPLEXER
Document Type and Number:
Japanese Patent JP2004241797
Kind Code:
A
Abstract:
To provide a multiplexer capable of maintaining high-speed and waveform quality and reducing the power consumption.
Level shift circuits 57 to 60, output polarity switching circuits 61 to 64, and output stop circuits 67 to 70 used in common to input circuits are located at a pre-stage of 2:1 multiplexers 75, 76.
Inventors:
NAKAYA YASUHIRO
Application Number:
JP2003025710A
Publication Date:
August 26, 2004
Filing Date:
February 03, 2003
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K17/00; H03M9/00; H04J3/04; (IPC1-7): H03M9/00; H03K17/00; H04J3/04
Attorney, Agent or Firm:
Tetsuo Hirado