Title:
SPECIFIED PATTERN DATA BLOCK COUNTING CIRCUIT
Document Type and Number:
Japanese Patent JP3389679
Kind Code:
B2
Abstract:
PURPOSE: To provide the specified pattern data block counting circuit of simple constitution whose circuit scale is small by providing a count-up control means.
CONSTITUTION: The count-up control means 150 transmits signals for count-up to a counting means 180 when all the bits of a specified pattern are equal with each other in a computer means 900 and also continues to transmit the signals for blocking the count-up from the point of time of detecting an inequality in bits until fixed reset is applied at the time of inequality. By the constitution, the comparator means 900 is turned to the constitution for comparing the specified pattern with a pattern for reference set beforehand for instance and obtaining and outputting the AND of the timing pulses of the respective bits of the specified pattern and a compared result. Thus, by using an AND circuit, this specified pattern data block counting circuit of the simple constitution whose circuit scale is small is obtained.
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Inventors:
Masao Nakano
Za ya Hisayoshi
Za ya Hisayoshi
Application Number:
JP12383694A
Publication Date:
March 24, 2003
Filing Date:
June 06, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04Q3/00; H04L12/26; H04L12/28; H04L12/70; (IPC1-7): H04L12/56
Domestic Patent References:
| JP5344145A | ||||
| JP575639A | ||||
| JP4242346A |
Attorney, Agent or Firm:
Junichi Yokoyama