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Title:
STACKED CHIP INDUCTOR
Document Type and Number:
Japanese Patent JPH07169621
Kind Code:
A
Abstract:

PURPOSE: To reduce the stress of a chip body at the time of burning of an external electrode by having a coil, where conductor patterns are superposed in the direction of stacking, and extending both ends of this conductor pattern to two sides nearly vertical to the direction of stacking, and forming an external electrode terminal only at these two sides.

CONSTITUTION: This is a stacked chip inductor, where a magnetic substance printed layer, a magnetic substance green sheet, a dielectric printed layer, or a dielectric green sheet, and a printed conductor pattern are stacked and baked integrally, and this stacked chip inductor has a coil where conductor pattern are stacked in the direction of stacking, and both ends of this conductor pattern are extended to two sides 2a and 2b nearly vertical to the direction of stacking, and external electrode terminals are formed only at the two sides 2a and 2b. Hereby, the occurrence of cracks by the stress to the chip body 1, which occurs at baking of metallic paste, can be prevented, and a highly reliable stacked chip inductor can be gotten.


Inventors:
KURIHARA KOICHIRO
TSUCHIDA HIROSHI
NUMATA TOSHIO
Application Number:
JP31300693A
Publication Date:
July 04, 1995
Filing Date:
December 14, 1993
Export Citation:
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Assignee:
HITACHI METALS LTD
International Classes:
H01F27/29; H01F17/00; (IPC1-7): H01F17/00; H01F27/29
Attorney, Agent or Firm:
Oba Mitsuru



 
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