PURPOSE: To obtain a static type transfer gate sequential circuit capable of performing the same high speed operation as a dynamic type and coping with a low speed operation.

CONSTITUTION: The static type transfer gate sequential circuit has a transfer gate TG, two inverters V1, V2, an input terminal D, an output terminal QB and a clock input terminal CC. One end of the transfer gate TG is connected with the input terminal D, the other end of the transfer gate TG is connected with the input terminal of the inverter V1, the output terminal of the inverter 1 is connected with the input terminal of the output terminal QB and the inverter V2 and the output terminal of the inverter 2 is connected with the input terminal of the inverter V1, respectively.