To provide a step-up circuit which can reduce a layout area of a MOS transistor concerning a step-up capability and which perform a step-up operation certainly at a starting time.
The step-up circuit includes the MOS transistors M1-M4 connected in series between an output voltage line 13 and a common connecting line 14 to perform a positive step-up operation of an input voltage VDD. The MOS transistors M1-M3 consist of ordinary P-type MOS transistors, and the MOS transistor M4 consists of an ordinary N-type MOS transistor. The MOS transistors M21-M24 are connected in series between the output voltage line 13 and the common connecting line 14 to perform a positive step-up operation of the input voltage VDD in parallel with the MOS transistors M1-M4. The MOS transistor M21 consists of an ordinary P-type MOS transistor, and the MOS transistor M24 consists of an ordinary N-type MOS transistor. On the other hand, the MOS transistors M22, M23 consist of N-type MOS transistors of a triple well structure.
Yoshiaki Naito
Cui Shu Tetsu
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