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Title:
SUM CHECKING SYSTEM
Document Type and Number:
Japanese Patent JPS59153244
Kind Code:
A
Abstract:

PURPOSE: To attain high speed processing by executing dividedly the sum value calculation of a user's program in plural times, executing the user's program on the basis of the divided sum calculation, and after the completion of the calculation, comparing the stored sum value with the calculated value.

CONSTITUTION: When a programmable controller starts to operate, a system is initialized, a program console part 5 sets up a progam mode to execute program processing such as the input of the program. After completing the processing, the program mode is released and the sum value of the inputted user's program is calculated and stored in a memory 3 as the value to be compared. Then, timer interruption for checking the sum is started and one byte of the user's program is added to the calculated value of the sum value. The address of the user's program is updated, the user's program is executed and one byte is added to the calculated value of the sum value. The final calculation value is found out by repeating said calculation and compared with the set value of the memory 3. Thus, sum checking can be executed at a high speed.


Inventors:
SUKIMOTO YASUYUKI
TAKINAMI KOUJI
ITANO YASUJI
Application Number:
JP2806883A
Publication Date:
September 01, 1984
Filing Date:
February 21, 1983
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F11/10; (IPC1-7): G06F11/10
Domestic Patent References:
JPS57174748A1982-10-27
Attorney, Agent or Firm:
Nakamura Shigenobu



 
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