Title:
SWITCHED CAPACITOR MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JPS6221317
Kind Code:
A
Abstract:
A switched-capacitor multiplier circuit is described for multiplying an information signal x(t) by a bipolar carrier signal d(t), comprising a distributed multiplier circuit (20) with which the bipolar carrier signal is normally associated. To reduce offset voltages in the output signal caused by the operational amplifiers used and caused as a result of clock feed-through, it is not the bipolar carrier signal itself, but a full-wave rectified version thereof that is associated with the distributed multiplier circuit, whilst the output signal of this circuit is applied to an auxiliary multiplier circuit (4) multiplying this output signal by + 1 or -1 dependent on the instantaneous polarity of the bipolar carrier signal d(t). The offset vottage is thereby transposed to a frequency which is at least equal to the fundamental frequency of the carrier signal so that, if desired, it can be suppressed with the aid of a suitably chosen low-pass filter (5) without the desired signal being affected thereby.
Inventors:
ARUTOURU HERUMANUSU MARIA FUAN
Application Number:
JP16484186A
Publication Date:
January 29, 1987
Filing Date:
July 15, 1986
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G06G7/16; H03D1/22; H03H19/00; H03L7/085; (IPC1-7): G06G7/16; H03D1/22; H03H19/00; H03L7/08
Attorney, Agent or Firm:
Akihide Sugimura